The following two papers has been accepted for publication in IEICE Transactions on Electronics, Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology.
- Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,” IEICE Transactions on Electronics, Apr. 2013 (to appear).
- Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,” IEICE Transactions on Electronics, Apr. 2013 (to appear).