Monthly Archives: June 2016

Article on our DAC2016 paper

Posted on Thursday June 23rd, 2016 by ts

Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.

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A paper presented at DAC2016

Posted on Wednesday June 15th, 2016 by ts

Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading →

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SISPAD2016: paper accepted

Posted on Monday June 13th, 2016 by hiromoto

The paper below has been accepted for presentation in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). This is a joint work with laboratory of Advanced Electrical Systems Theory, Department of Electrical Engineering at Kyoto University. Yohei Nakamura, … Continue reading →

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ISCAS2016

Posted on Wednesday June 1st, 2016 by ts

Sorry, this entry is only available in 日本語.

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