Monthly Archives: June 2016
Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.
Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading
The paper below has been accepted for presentation in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). This is a joint work with laboratory of Advanced Electrical Systems Theory, Department of Electrical Engineering at Kyoto University. Yohei Nakamura, … Continue reading
Sorry, this entry is only available in 日本語.