Monthly Archives: February 2016
Lab tour for prospective senior students in EE has been held on Feb. 24, 2016. Students who are interested in joining our group but missed the lab tour, contact us via e-mail.
The following paper has been accepted for presentation in DAC 2016 (ACM/IEEE Design Automation Conference). Hiromitsu Awano and Takashi Sato, “Efficient Transistor-level Timing Yield Estimation via Line Sampling,” ACM/IEEE Design Automation Conference (DAC), accepted for presentation, Jun 2016. (Austin, TX)
A paper is accepted for presentation in GLSVLSI 2016 (Boston, MA). Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation,” Great Lakes Symposium on VLSI (GLSVLSI) (Boston, MA), … Continue reading
The following paper has been accepted for presentation in ISQED 2016. Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, and Takashi Sato: “Nonlinear Delay-Table Approach for Full-Chip NBTI Degradation Prediction,” in Proc. of International Symposium on Quality Electronic Design (ISQED) … Continue reading
The following papers are accepted for publication in TAU workshop 2016, congratulations! Hiromitsu Awano and Takashi Sato: “Efficient Transistor-Level Timing Yield Estimation via Line Sampling,” in Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) (Santa Rosa, CA), Mar. 2016 … Continue reading
The paper below has been accepted for ISCAS2016, which will be held in May 2016 at Montreal, Canada. Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Physically Unclonable Function using RTN-Induced Delay Fluctuation in Ring Oscillators,” IEEE International Symposium … Continue reading