Yearly Archives: 2016

(日本語) 2016年 電子情報通信学会 ソサイエティ大会（2日目）

Posted on Friday September 30th, 2016 by hiromoto

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(日本語) 2016年 電子情報通信学会 ソサイエティ大会（１日目）

Posted on Friday September 30th, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) 情報処理学会コンピュータサイエンス領域奨励賞 受賞

Posted on Saturday September 17th, 2016 by hiromoto

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(日本語) SLDM研究会 最優秀発表学生賞 受賞

Posted on Saturday September 17th, 2016 by hiromoto

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(日本語) DAシンポジウム2015優秀発表学生賞 受賞

Posted on Saturday September 17th, 2016 by hiromoto

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(日本語) DAシンポジウム2016

Posted on Friday September 16th, 2016 by hiromoto

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(日本語) SISPAD2016

Posted on Tuesday September 13th, 2016 by hiromoto

Dr. Shintani presented his paper at the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) held in Nuremberg, Germany. SISPAD has provided an international forum for the presentation of leading-edge research and development results in the area of … Continue reading →

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Papers accepted for presentation in WiPDA 2016

Posted on Tuesday September 13th, 2016 by hiromoto

The following papers have been accepted for presentation in WiPDA (the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications). Michihiro Shintani, Kazuki Oishi, Rui Zhou, Masayuki Hiromoto, and Takashi Sato: “A Circuit Simulation Model for V-Groove SiC Power … Continue reading →

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Paper accepted for presentation in ASP-DAC 2017

Posted on Monday September 5th, 2016 by hiromoto

The following paper has been accepted for presentation in ASP-DAC 2017 (Asia and South Pacific Design Automation Conference). Acceptance rate 31%=111/358. Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Efficient Circuit Failure Probability Calculation Along Product Lifetime Considering Device Aging,” 22nd … Continue reading →

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Paper accepted for publication in Journal of Electronic Testing: Theory and Applications

Posted on Wednesday August 24th, 2016 by hiromoto

Following paper has been accepted for publication in Journal of Electronic Testing: Theory and Applications (JETTA). Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, and Takashi Sato: “Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing,” Journal … Continue reading →

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