(日本語) VLSI設計技術研究会2020年3月

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A paper has been accepted for publication in IEEE Transactions on Information Forensics & Security

The following paper has been accepted for publication in IEEE Transactions on Information Forensics & Security.

  • Yue Zheng, Xiaojin Zhao, Takashi Sato, Yuan Cao, and Chip-Hong Chang: “Ed-PUF: Event-driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System,” IEEE Transactions on Information Forensics & Security, (to appear)
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IEICE VLD Excellent Student Author Award for ASP-DAC 2020

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CVPR2020: paper accepted

The following paper has been accepted for presentation in the Computer Vision and Pattern Recognition (CVPR) 2020 (Acceptance rate 22.1%=1470/6656).
This work is in collaboration with the JSPS visiting scholar Associate Professor Yiyu Shi from the University of Notre Dame.

  • Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, and Takashi Sato:
    “ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition,” in Proc. IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) (Seattle, USA), June 2020 (to appear).
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A paper accepted for publication in IEEE Transactions on Semiconductor Manufacturing

  • Hiroki Tsukamoto, Michihiro Shintani and Takashi Sato:
    “Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs,” IEEE Transactions on Semiconductor Manufacturing, (to appear).
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DAC2020: paper accepted

The following paper has been accepted for presentation in Design Automation Conference 2020. The paper presentation from our group in the DAC conference is five years in a row.

  • Akira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian and Takashi Sato, “Clustering approach for solving traveling salesman problems via Ising model based solver,” in Proc. ACM/IEEE Design Automation Conference (DAC), to appear.
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ASPDAC2020

A master course student, Yuki Kume, made a presentation in ASPDAC2020 held at China National Convention Center, Beijing, China.

Echo State Network (ESN), which is a kind of recurrent neural network (RNN), has recently attracted many attentions. The weights of the input and middle layers of the ESN are randomly determined constants that need not to go through a training process. ESN has low calculation cost compared with LSTM, an other type of RNN, and thus it is suitable for hardware implementation. In this presentation, we proposed a method of expressing random weights by a MOSFET crossbar array circuit, a method of controlling the feedback parameters to satisfy convergence requirements, and an architecture of ESN to enhance accuracy under the nonidealities due to the hardware implementation. Experiments and evaluations has shown that the proposed “Dual-MOS-ESN” achieves equal accuracy as the software ESN.

  • Yuki Kume, Song Bian, and Takashi Sato, “A tuning-free hardware reservoir based on MOSFET crossbar array for practical echo state network implementation,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.458-463, January 2020.
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ECAI2020: paper accepted

The following paper has been accepted for presentation in the European Conference on Artificial Intelligence (ECAI) 2020 (Acceptance rate 26.8%=365/1363).
This work is in collaboration with the JSPS visiting scholar Associate Professor Yiyu Shi from the University of Notre Dame.

  • Song Bian, Weiwen Jiang, Qing Lu, Yiyu Shi, and Takashi Sato:
    “NASS: Optimizing Secure Inference via Neural Architecture Search,” European Conference on Artificial Intelligence (ECAI) (Santiago de Compostela, Spain), June 2020 (to appear).
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ISCAS2020: paper accepted

The following paper has been accepted for presentation in the IEEE International Symposium on Circuits and Systems (ISCAS) 2020. The conference will be held in May 17-20, 2020 in Seville, Spain. This work is in collaboration with the Nanjing University of Aeronautics and Astronautics.

  • Dur E Shahwar Kundi, Song Bian, Ayesha Khalid, Chenghua Wang, Maire O’Neill, and Weiqiang Liu:
    “AxMM: Area and Power Efficient Approximate Modulo Multiplier for R-LWE Cryptosystem,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS) (Seville, Spain), May 2020 (to appear).
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Lab tour for EE junior students

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