Photos taken after graduation ceremony for undergraduates. Congratulations!
Two students, Tsukamoto and Saito, presented papers in the 32nd IEEE International Conference on Microelectronic Test Structure (ICMTS) 2019, at the International conference center in Kitakyushu, which was held during March 18-21, 2019.
- Hiroki Tsukamoto, Michihiro Shintani, and Takashi Sato, “Study on statistical parameter extraction of power MOSFET model by principal component analysis,” in Proc. IEEE International Conference on Microelectronic Test Structures (ICMTS), pp.107-112, March 2019.
- Michiaki Saito, Michihiro Shintani, Kazunori Kuribara, Yasuhiro Ogasahara, and Takashi Sato, “A compact model of I-V characteristic degradation for organic thin film transistors,” in Proc. IEEE International Conference on Microelectronic Test Structures (ICMTS), pp.194-199, March 2019.
In the annual meeting of IEEE Kansai Section held on February 22nd, 2019, Yuki Tanaka received the IEEE Kansai Section Student Paper Award for his following publication.
- Yuki Tanaka, Song Bian, Masayuki Hiromoto, and Takashi Sato:
“Coin Flipping PUF: A Novel PUF with Improved Resistance Against Machine Learning Attacks,” IEEE Transactions Circuits and Systems II: Express Briefs, Vol.65, No.5, pp.602-606, May 2018.
Lab tour was held on 1pm-3pm Feb. 21, 2019. Please feel free to visit us at any time or send an e-mail for an appointment, if you missed the chance.
The following paper has been accepted for presentation in DAC2019（ACM/IEEE Design Automation Conference 2019） (acceptance rate 24.8%=202/815). Conguratulations!!
- Song Bian, Masayuki Hiromoto, and Takashi Sato, “Filianore: Better multiplier architectures for LWE-based post-quantum key exchange,” in Proc. ACM/IEEE Design Automation Conference (DAC), to appear
A Ph.D student, Song gave an oral presentation in Asia and South Pacific Design Automation Conference (ASP-DAC) 2019 held at the National Musium of Science and Art during Jan. 21-24, 2019. (The presentation was on Jan. 25th.)
His presentation is about a secure filter, specically, a secure version of the naive Bayesian filter (NBF) is proposed utilizing partially homomorphic encryption (PHE) scheme. SNBF can be implemented with only the additive homomorphism from the Paillier system, and we derive new techniques to reduce the computational cost of PHE-based SNBF. In the experiment, we implemented SNBF both in software and hardware. Compared to the best existing PHE scheme, we achieved 1,200x and 398,840x runtime reduction for CPU and ASIC implementations, repsectively, with additional 1,919x power reduction on the designated hardware multiplier. Our hardware implementation is able to classify an average-length email in 0.5s, making it one of the most practical NBF schemes to date.
- Song Bian, Masayuki Hiromoto, and Takashi Sato, “Towards practical homomorphic email filtering: A hardware-accelerated secure naive Bayesian filter,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.621-626, January 2019.