Author Archives: ts

(日本語) SSDM2017

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(日本語) Cheng Zhuo先生講演会

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JST Fair 2017

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Paper published in IEEE Trans. VLSI

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(日本語) Jerald Yoo先生講演会

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ICMTS 2017

Mr. Oishi presented his paper at International Conference on Microelectronic Test Structures (ICMTS) 2017 held in Grenoble, France. Mr. Oishi’s talk was about input capacitance measurement of power MOSFETs. The modeling of the input capacitance is crucial for the simulation … Continue reading

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ACM/IEEE ASPDAC 2017

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Paper accepted for publication in IEEE Transactions on Very Large Scale Integration Systems

The following paper has been accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Hiromitsu Awano, Shumpei Morita, and Takashi Sato: “Scalable device array for statistical characterization of BTI-related parameters,” IEEE Transactions on Very Large Scale … Continue reading

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Article on our DAC2016 paper

Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.

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A paper presented at DAC2016

Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading

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