Author Archives: ts

(日本語) SSDM2017

Posted on Friday September 22nd, 2017 by ts

Sorry, this entry is only available in 日本語.

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(日本語) Cheng Zhuo先生講演会

Posted on Saturday September 16th, 2017 by ts

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JST Fair 2017

Posted on Saturday September 2nd, 2017 by ts
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Paper published in IEEE Trans. VLSI

Posted on Tuesday August 1st, 2017 by ts

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(日本語) Jerald Yoo先生講演会

Posted on Monday June 12th, 2017 by ts

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ICMTS 2017

Posted on Tuesday April 4th, 2017 by ts

Mr. Oishi presented his paper at International Conference on Microelectronic Test Structures (ICMTS) 2017 held in Grenoble, France. Mr. Oishi’s talk was about input capacitance measurement of power MOSFETs. The modeling of the input capacitance is crucial for the simulation … Continue reading →

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ACM/IEEE ASPDAC 2017

Posted on Wednesday January 25th, 2017 by ts

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Paper accepted for publication in IEEE Transactions on Very Large Scale Integration Systems

Posted on Thursday January 5th, 2017 by ts

The following paper has been accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Hiromitsu Awano, Shumpei Morita, and Takashi Sato: “Scalable device array for statistical characterization of BTI-related parameters,” IEEE Transactions on Very Large Scale … Continue reading →

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Article on our DAC2016 paper

Posted on Thursday June 23rd, 2016 by ts

Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.

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A paper presented at DAC2016

Posted on Wednesday June 15th, 2016 by ts

Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading →

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